Answered>Order 27558
Source files: you may copy and paste from this document. The order in this file is: tb.v, latchff.v (for Verilog) and tb.vhd, latchff.vhd (for VHDL).
// ————————–=————————————–
// University of North Carolina Charlotte
// ————————–=————————————–
// Copyright (c) 2007 by University of North Carolina Charlotte
// Department of Engineering Technology
//
// This design is the property of the Department of Engineering
// Technology in the Lee College of Engineering at the University
// of North Carolina Charlotte. Possession or use of this design
// (or any derivative) requires written consent of the Department
// of Engineering Technology, UNCC.
// ————————–=————————————–
// tb.v : Testbench for latches and flipflops
// SUBSYSTEM : —
// CHIP : —
// ————————–=————————————–
// owner : Sam Mitchum, Maciej Noras
// department : Engineering Technology
// ————————–=————————————–
// Revision History
// 2007 Apr 04 – smitchum – design started
// 2018 Apr 18 – mnoras – design revision and verification
// ————————–=————————————–
// Function: This module is a test bench to illustrate operation of
// latches and flipflops.
// ————————–=————————————–
`timescale 1 ns / 1 ps // time reference / precision
//
// DEFINITIONS – you can use these to define constants for the HDL
//
`define HALF_PERIOD 25 // half clock period in ns
`define CLOCKS_TO_RUN 129 // stop after this many clocks
//————————————————————–
// Module, ins and outs
// [Verilog: module name and file name should be the same]
//————————————————————–
module tb;
// nets for connecting to the latches and flipflops
wire tb_SRQ;
wire tb_SRnQ;
wire tb_nSnRQ;
wire tb_nSnRnQ;
wire tb_DQ;
wire tb_DnQ;
reg tb_hS; // these are registered – that is they
reg tb_hR; // hold their value until reassigned
reg tb_Ck;
reg tb_hD;
// nets (wires) for normal test bench functions…
reg tb_clk; // clock – square wave
reg tb_rst; // reset – we’ll need it someday 🙂
reg [15:0] tb_timer; // timer for the test bench
// instantiate the latches and flipflops
latchff LogicToTest
(
.SRQ (tb_SRQ),
.SRnQ (tb_SRnQ),
.nSnRQ (tb_nSnRQ),
.nSnRnQ (tb_nSnRnQ),
.DQ (tb_DQ),
.DnQ (tb_DnQ),
.hS (tb_hS),
.hR (tb_hR),
.Clk (tb_Ck),
.hD (tb_hD)
);
//
// initial block is executed once and only once at startup
//
initial
begin
tb_rst = 1’b0;
tb_clk = 1’b0; // start the clock at 0
#1 tb_rst = 1’b1; // assert reset signal
#10 tb_rst = 1’b0; // after 10ns deassert reset
end
//
// Create a square wave on the clock signal
//
always
begin
#`HALF_PERIOD tb_clk = ~tb_clk;
end
//
// Run the timer – increment every clock and clear on reset
//
always @ (posedge tb_clk or posedge tb_rst)
begin
if (tb_rst == 1’b1)
begin
tb_timer = 0;
end
else
begin
tb_timer = tb_timer + 1;
end
end
//
// Run the test bench – wiggle the outputs and wait for timeout
//
always @ (tb_timer)
begin
if (tb_timer <= `CLOCKS_TO_RUN)
begin
tb_hS = tb_timer[3] & tb_timer[2] & ~tb_timer[1];
tb_hR = ~tb_timer[3] & ~tb_timer[2] & tb_timer[1];
tb_hD = tb_timer[3];
tb_Ck = tb_timer[1];
end
else
begin
$display (“Stopping on the %d clock”, tb_timer);
$stop; // special command to stop simulation
end
end
endmodule // tb
This next file is latchff.v – about two pages
// ————————–=————————————–
// University of North Carolina Charlotte
// ————————–=————————————–
// Copyright (c) 2007 by University of North Carolina Charlotte
// Department of Engineering Technology
//
// This design is the property of the Department of Engineering
// Technology in the Lee College of Engineering at the University
// of North Carolina Charlotte. Possession or use of this design
// (or any derivative) requires written consent of the Department
// of Engineering Technology, UNCC.
// ————————–=————————————–
// LatchFF.v : logic for testing latches and flipflops
// SUBSYSTEM : —
// CHIP : —
// ————————–=————————————–
// owner : Sam Mitchum, Maciej Noras
// department : Engineering Technology
// ————————–=————————————–
// Revision History
// 2007 Apr 04 – smitchum – design started
// 2018 Apr 18 – mnoras – design revision and verification
// **************************=**************************************
//
// G E N E R A L D O C U M E N T A T I O N
//
// function: LatchFF implements latches and flipflops in Verilog.
// It is intended as a supplement to ETEE1231.
//
// timing: standard ‘LS timing
//
// outputs: SRQ: Active high S-R latch output
// SRnQ: Active high S-R latch inverted output
// nSnRQ: Active low S-R latch output
// nSnRnQ: Active low S-R latch inverted output
// DQ: Clocked edge triggered D flipflop output
// DnQ: Clocked edge triggered D flipflop inverted out
//
// inputs: hS: Active high SET
// hR: Active high RESET
// Clk: Clock
// hD: Active high D signal for flipflop
//
// synthesis: n/a
//
// **************************=**************************************
`timescale 1 ns / 1 ps // reference time unit / precision
//————————————————————–
// Module and input / output definition
//————————————————————–
module latchff
(
SRQ,
SRnQ,
nSnRQ,
nSnRnQ,
DQ,
DnQ,
hS,
hR,
Clk,
hD
);
output SRQ; // then we define them as outputs or inputs
output SRnQ;
output nSnRQ;
output nSnRnQ;
output DQ; // note the new language – the output DQ is also
reg DQ; // registered – that is it holds its value
output DnQ; // until explicitly changed (so does DnQ)
reg DnQ;
input hS;
input hR;
input Clk;
input hD;
//————————————————————–
// Architecture
//————————————————————–
assign #(6.5:9.5:21.5) SRQ = ~(hR | SRnQ);
assign #(6.5:9.5:21.5) SRnQ = 1’b0; // you fix this
assign #(6:9:18) nSnRQ = ~(~hS & nSnRnQ);
assign #(6:9:18) nSnRnQ = 1’b0; // you fix this
always @(posedge Clk)
begin
#(10:17:32) // min:typ:max delay for 74LS74A
DQ <= hD;
DnQ <= 1’b0; // you fix this
end
endmodule // latchff
_______________________________________________________________________
Now the VHDL files: First tb.vhd about three pages
— ————————–=————————————–
— University of North Carolina Charlotte
— ————————–=————————————–
— Copyright (c) 2007 by University of North Carolina Charlotte
— Department of Engineering Technology
—
— This design is the property of the Department of Engineering
— Technology in the Lee College of Engineering at the University
— of North Carolina Charlotte. Possession or use of this design
— (or any derivative) requires written consent of the Department
— of Engineering Technology, UNCC.
— ————————–=————————————–
— tb.vhd : Testbench for testing latches and flipflops
— SUBSYSTEM : —
— CHIP : —
— ————————–=————————————–
— owner : Sam Mitchum, Maciej Noras
— department : Engineering Technology
— ————————–=————————————–
— Revision History
— 2007 Apr 04 – smitchum – design started
— 2018 Apr 18 – mnoras – design revision and verification
— ————————–=————————————–
— Function: This module is meant to exercise the latches and
— flipflops to illustrate proper operation.
— ————————–=————————————–
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE std.standard.all;
USE std.textio.all;
USE work.all;
—————————————————————-
— Entity
—————————————————————-
ENTITY tb IS
END tb;
—————————————————————-
— Architecture
—————————————————————-
ARCHITECTURE bench OF tb IS
COMPONENT latchff
PORT (
SRQ : OUT STD_LOGIC;
SRnQ : OUT STD_LOGIC;
nSnRQ : OUT STD_LOGIC;
nSnRnQ : OUT STD_LOGIC;
DQ : OUT STD_LOGIC;
DnQ : OUT STD_LOGIC;
hS : IN STD_LOGIC;
hR : IN STD_LOGIC;
hD : IN STD_LOGIC;
Clk : IN STD_LOGIC
);
END COMPONENT;
—
— signals for connecting to the unit under test
—
SIGNAL tb_SRQ : STD_LOGIC;
SIGNAL tb_SRnQ : STD_LOGIC;
SIGNAL tb_nSnRQ : STD_LOGIC;
SIGNAL tb_nSnRnQ : STD_LOGIC;
SIGNAL tb_DQ : STD_LOGIC;
SIGNAL tb_DnQ : STD_LOGIC;
SIGNAL tb_hS : STD_LOGIC;
SIGNAL tb_hR : STD_LOGIC;
SIGNAL tb_hD : STD_LOGIC;
SIGNAL tb_Ck : STD_LOGIC;
—
— signals for the testbench
—
SIGNAL tb_clk : STD_LOGIC := ‘0’; — clock signal
SIGNAL tb_rst : STD_LOGIC := ‘0’; — reset signal
SIGNAL tb_timer: UNSIGNED (15 DOWNTO 0) := “0000000000000000”;
—
— DEFINITIONS – you can use these to define constants for the HDL
—
CONSTANT HALF_PERIOD : TIME := 25 ns; — half clock ns
CONSTANT CLOCKS_TO_RUN : UNSIGNED(15 DOWNTO 0) := “0000000010000010”;
—————————————————————-
— Finished with declarations: start of architecture proper
—————————————————————-
BEGIN
— first instantiate the unit to test
UUT: latchff
PORT MAP (
SRQ => tb_SRQ,
SRnQ => tb_SRnQ,
nSnRQ => tb_nSnRQ,
nSnRnQ => tb_nSnRnQ,
DQ => tb_DQ,
DnQ => tb_DnQ,
hS => tb_hS,
hR => tb_hR,
hD => tb_hD,
Clk => tb_Ck
);
—
— reset signal: after 10ns release it
—
MyReset: PROCESS
BEGIN
tb_rst <= ‘1’;
WAIT FOR 10 ns;
tb_rst <= ‘0’;
WAIT;
END PROCESS MyReset;
—
— Create a squarewave on the clock signal
MakeClock: PROCESS
BEGIN
WAIT FOR HALF_PERIOD;
tb_clk <= NOT (tb_clk);
IF (tb_timer > CLOCKS_TO_RUN) THEN
WAIT;
END IF;
END PROCESS MakeClock;
—
— Run the timer – increment every clock and clear on reset
—
RunTimer: PROCESS (tb_clk, tb_rst)
BEGIN
IF ((tb_rst’EVENT) AND (tb_rst = ‘1’)) THEN
tb_timer <= “0000000000000000”;
ELSE
IF ((tb_clk’EVENT) AND (tb_clk = ‘1’)) THEN
tb_timer <= tb_timer + “0000000000000001”;
END IF;
END IF;
END PROCESS RunTimer;
—
— Run the test bench – wiggle the outputs and wait for timeout
—
TheTB: PROCESS (tb_timer)
BEGIN
tb_hS <= tb_timer(3) AND tb_timer(2) AND (NOT (tb_timer(1)));
tb_hR <= (NOT (tb_timer(3))) AND (NOT (tb_timer(2))) AND tb_timer(1);
tb_hD <= tb_timer(3);
tb_Ck <= tb_timer(1);
END PROCESS TheTB;
END; — ARCHITECTURE bench
And finally, the latchff.vhd file (about two pages)
— ————————–=————————————–
— University of North Carolina Charlotte
— ————————–=————————————–
— Copyright (c) 2007 by University of North Carolina Charlotte
— Department of Engineering Technology
—
— This design is the property of the Department of Engineering
— Technology in the Lee College of Engineering at the University
— of North Carolina Charlotte. Possession or use of this design
— (or any derivative) requires written consent of the Department
— of Engineering Technology, UNCC.
— ————————–=————————————–
— latchff.vhd : logic for demonstrating latches and flipflops
— SUBSYSTEM : —
— CHIP : —
— ————————–=————————————–
— owner : Sam Mitchum, Maciej Noras
— department : Engineering Technology
— ————————–=————————————–
— Revision History
— 2007 Apr 04 – smitchum – design started
— 2018 Apr 18 – mnoras – design revision and verification
— **************************=**************************************
—
— G E N E R A L D O C U M E N T A T I O N
—
— function: latchff – This HDL design will be used to illustrate
— latch and flipflop operation
—
— timing: ‘LS typical timing used
—
— outputs: SRQ and SRnQ outputs from active high SR latch
— nSnRQ and nSnRnQ outputs from active low SR latch
— DQ and DnQ outputs from D flipflop
—
— inputs: hS and hR Set and Reset inputs
— hD and Clk Data input and Clock for D flipflop
—
— synthesis: n/a
—
— **************************=**************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE std.standard.all;
USE std.textio.all;
USE work.all;
—————————————————————-
— Entity
—————————————————————-
ENTITY latchff IS
PORT (
SRQ : OUT STD_LOGIC;
SRnQ : OUT STD_LOGIC;
nSnRQ : OUT STD_LOGIC;
nSnRnQ : OUT STD_LOGIC;
DQ : OUT STD_LOGIC;
DnQ : OUT STD_LOGIC;
hS : IN STD_LOGIC;
hR : IN STD_LOGIC;
hD : IN STD_LOGIC;
Clk : IN STD_LOGIC
);
END latchff;
—————————————————————-
— Architecture
—————————————————————-
ARCHITECTURE behav OF latchff IS
— Some signals for solving the “can’t read output” stuff
SIGNAL i_SRQ : STD_LOGIC;
SIGNAL i_SRnQ : STD_LOGIC;
SIGNAL i_nSnRQ : STD_LOGIC;
SIGNAL i_nSnRnQ : STD_LOGIC;
BEGIN
i_SRQ <= NOT (hR OR i_SRnQ) AFTER 10 ns;
SRQ <= i_SRQ;
i_SRnQ <= ‘0’ AFTER 10 ns;
SRnQ <= i_SRnQ;
i_nSnRQ <= NOT ((NOT (hS)) AND i_nSnRnQ) AFTER 9 ns;
nSnRQ <= i_nSnRQ;
i_nSnRnQ <= ‘0’ AFTER 9 ns;
nSnRnQ <= i_nSnRnQ;
MyDFF: PROCESS (Clk)
BEGIN
IF ((Clk’EVENT) AND (Clk = ‘1’)) THEN
DQ <= hD AFTER 15 ns;
DnQ <= ‘0’ AFTER 15 ns;
END IF;
END PROCESS MyDFF;
END; — ARCHITECTURE latchff
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